| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for reducing a load for a resist patterning process, and for reducing the dielectric constant of the interlayer insulating film in forming a dual damascene structure in an interlayer insulating film. SOLUTION: A first insulating film (SiOC film) 6, a second insulating film (organic film) 7, a first mask formation layer (SiOC film) 21, a second mask formation layer (SiO<SB>2</SB>film) 22, and a third mask formation layer (SiN film) 23, are successively formed; and the third mask formation layer 23 is patterned so that a third mask 23A having a wiring groove pattern can be formed. A resist mask 12 is formed at the upper part, and etched to the second insulating film 7 so that a connection hole can be opened. The second mask formation layer 22 is etched from the upper part of the third mask so that a second mask having a wiring groove pattern can be formed, and the first insulating film 6 is etched to the middle so that the connection hole can be dug. The first mask formation layer 21 is etched from the upper part of the second mask so that the first mask having the wiring groove pattern can be formed, and the first insulating film 6 is etched so that the connection hole can be opened. The second insulating film 7 is etched from the first mask to the second mask so that a wiring groove 16 can be formed. COPYRIGHT: (C)2005,JPO&NCIPI
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