发明名称
摘要 PROBLEM TO BE SOLVED: To optimize the inserting position and the number of transfer gate in a circuit where a bit line is divided through a transfer gate by constituting a designing system for a memory circuit of a memory generating subsystem and a data analyzing subsystem. SOLUTION: The designing system for a memory circuit comprises memory generating subsystem 1 and a data analyzing subsystem 2. The memory generating subsystem 1 generates the circuit and layout of memory. The data analyzing subsystem 2 determines optimal number of insertion and inserting position of transfer gate by analyzing data stored in a memory. A memory circuit of low power consumption can be designed and generated automatically through communication of required data. Furthermore, power consumption of the memory circuit can be reduced depending on the use of a memory circuit being designed and generated and an optimal sense amplifier can be designed and generated depending on an address being accessed.
申请公布号 JP3682188(B2) 申请公布日期 2005.08.10
申请号 JP19990264491 申请日期 1999.09.17
申请人 发明人
分类号 G11C11/41;G06F17/50;G11C11/409;H01L21/8242;H01L27/108 主分类号 G11C11/41
代理机构 代理人
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