发明名称 Virtual dual-port synchronous RAM architecture
摘要 Disclosed is a virtual dual-port synchronous RAM device, system, and method, wherein the design requires minimal hardware cost compared with a dual-port RAM architecture or the traditional architecture used with a single-port RAM. Disclosed is a read/write memory device including means to accept signals from a first host and a second host, the first host having a first clock and the second host having a second clock, the signals including a first clock signal and a second clock, a clock switching means for switching between the first clock signal and the second clock signal, a single-port random access memory (RAM) module for storing data, and a RAM clock for synchronizing the clock signals with the RAM module.
申请公布号 US6928027(B2) 申请公布日期 2005.08.09
申请号 US20030686960 申请日期 2003.10.15
申请人 QUALCOMM INC 发明人 LI TAO
分类号 G06F13/16;G11C7/10;G11C8/00;G11C11/00;(IPC1-7):G11C11/00 主分类号 G06F13/16
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