发明名称 |
Bitline hard mask spacer flow for memory cell scaling |
摘要 |
The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
|
申请公布号 |
US6927145(B1) |
申请公布日期 |
2005.08.09 |
申请号 |
US20040770673 |
申请日期 |
2004.02.02 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
YANG JEAN Y.;RAMSBEY MARK T.;PARK JAEYONG;KAMAL TAZRIEN;LINGUNIS EMMANUIL H. |
分类号 |
H01L21/027;H01L21/761;H01L21/8246;H01L27/115;(IPC1-7):H01L21/761 |
主分类号 |
H01L21/027 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|