System clock synchronization circuit

摘要

A system clock synchronization circuit according to the present invention includes: a first synchronization and timing delay circuit synchronizing an input clock with a system clock and sending out a first signal which is obtained by delaying the synchronized signal by a first delay amount; an input data latching means for latching input data which changes at a first changing point of the input clock, the latching being in synchronization with a second changing point of the input clock; an input enable signal latching means for latching in synchronization with the input clock an input enable signal which is active when the input data is valid and inactive when the input data is invalid; and a mask signal generation circuit generating in synchronization with the first signal a mask signal which has a prescribed pulse width.