| 摘要 |
An interactive repeater insertion simulator (IRIS) system and method quickly and easily optimize the design of an integrated circuit (IC) interconnect for an electrical signal through the insertion of repeaters. The IRIS system utilizes the combination of a router, a repeater inserter, and a delay simulator to efficiently simulate repeater insertion. The router defines the route between more than one circuit and derives a first netlist. The first netlist is then sent to the repeater inserter to define the insertion of repeaters. A second netlist is outputted from the repeater inserter having thereupon one or more repeaters, inserted, and the physical locations of these repeaters along the interconnect for optimal performance, and minimum propagation delay. The delay simulator is then run on the second netlist to calculate the new interconnect delays. The interconnect delays may then be plotted or otherwise output for examination.
|
