发明名称 Wafer handling method for use in lithography patterning
摘要 A method utilizing a lithography system comprises a lithography patterning chamber, a wafer exchange chamber separated from the lithography patterning chamber by a first gate valve, and at least one alignment load-lock separated from the wafer exchange chamber by a second gate valve. The alignment load-lock includes an alignment stage that aligns a wafer during pump-down. The alignment load-lock can be uni-directional or bi-directional. The lithography system can include one or multiple alignment load-locks.
申请公布号 US6927842(B2) 申请公布日期 2005.08.09
申请号 US20040896057 申请日期 2004.07.22
申请人 ASML HOLDING N.V. 发明人 DEL PUERTO SANTIAGO E.;ROUX STEPHEN;KREUZER JUSTIN L.
分类号 G03B27/58;G03F7/20;G03F9/00;H01L21/00;H01L21/027;H01L21/677;H01L21/68;(IPC1-7):G03F27/32 主分类号 G03B27/58
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