| 摘要 |
The divider has three D flip-flops (U 1, U 2, U 3), where each D flip-flop receives a frequency (F e) to be divided. Loop connection between an output of one D flip-flop and its input or input of other D flip-flops has a single multiplexer. One D flip-flop controls charging of all the flip-flops during a period of frequency (F e). Each multiplexer has 2 inputs, 1 selection bit and 1 output and is integrated to one D flip-flop. |
