发明名称 |
A METHOD AND INTEGRATED CIRCUIT ARRANGED FOR FEEDING A TEST FORCING PATTERN ON A SINGLE SHARED PIN OF THE CIRCUIT |
摘要 |
An integrated circuit is forced into a test mode through executing the following steps: presenting a test forcing pattern on a subset of the circuit's external pins for driving the circuit to a test mode, presenting the electronic test forcing pattern to the circuit and finally executing the test proper. In particular, the following steps are implemented: presenting the pattern on a single pin in the form of an aggregate of a clocking sequence and a transition signalling data sequence as input data for an on-circuit storage element; clocking the storage element by a delayed version of the test forcing pattern; sequentially storing successive data parts of the test forcing pattern under control of successive clock parts of the delayed test forcing pattern; matching a predetermined string of the stored data parts versus a standard pattern, and upon finding a match driving the circuit to a test condition for then executing a test procedure. |
申请公布号 |
EP1157278(B1) |
申请公布日期 |
2005.08.03 |
申请号 |
EP20000979546 |
申请日期 |
2000.11.09 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
MELI, LOUIS, M. |
分类号 |
G01R31/28;G01R31/317;G01R31/3183;G01R31/3185;(IPC1-7):G01R31/317 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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