Semiconductor device and method for forming a semiconductor device using post gate stack planarization

摘要

Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.