发明名称 |
Method of forming a via contact structure using a dual damascene technique |
摘要 |
A method of forming a via contact structure using a dual damascene technique is provided. The method includes forming a lower interconnection line on a semiconductor substrate and sequentially forming an inter-metal dielectric layer and a hard mask layer on the semiconductor substrate having the lower interconnection line. The hard mask layer and the inter-metal dielectric layer are successivley patterned to form a via hole that exposes the lower interconnnection line. A sacrificial layer filling the via hole is formed on the hard mask layer. The sacrificial layer and the hard mask layer are patterned to form a first sacrificial layer pattern having an opening that crosses over the via hole and a second sacrificial layer pattern that remains in the via hole and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern. The inter-metal dielectric layer is partially etched using the hard mask pattern as an etching mask, thereby forming a trench in the inter-metal dielectric layer. The second sacrificial layer pattern is selectively removed to expose the the lower interconnection line.
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申请公布号 |
US6924228(B2) |
申请公布日期 |
2005.08.02 |
申请号 |
US20030748900 |
申请日期 |
2003.12.30 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM IL-GOO;HAH SANG-ROK |
分类号 |
H01L21/28;H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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