发明名称 |
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants |
摘要 |
A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
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申请公布号 |
US6925537(B2) |
申请公布日期 |
2005.08.02 |
申请号 |
US20030698130 |
申请日期 |
2003.10.31 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
BARROSO LUIZ A.;GHARACHORLOO KOUROSH;NOWATZYK ANDREAS;RAVISHANKAR MOSUR K.;STETS, JR. ROBERT J. |
分类号 |
G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
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