发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING MEMORY CELL SECTION HAVING CAPACITOR OVER BITLINE STRUCTURE AND WITH THE MEMORY AND PERIPHERAL SECTIONS HAVING CONTACT PLUG STRUCTURES CONTAINING A BARRIER FILM AND EFFECTING ELECTRICAL CONTACT WITH MISFETS OF BOTH MEMORY AND PERIPHERAL SECTIONS |
摘要 |
The sheet resistance of a gate electrode 8 A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL<SUB>1</SUB>, BL<SUB>2 </SUB>are, respectively, 2 Omega/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8 A (the word line WL) or the bit lines BL<SUB>1</SUB>, BL<SUB>2 </SUB>by which the number of the steps of manufacturing the DRAM can be reduced.
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申请公布号 |
US6924525(B2) |
申请公布日期 |
2005.08.02 |
申请号 |
US20030642743 |
申请日期 |
2003.08.19 |
申请人 |
HITACHI, LTD. |
发明人 |
NARUI SEIJI;UDAGAWA TETSU;KAJIGAYA KAZUHIKO;YOSHIDA MAKOTO |
分类号 |
H01L21/768;H01L21/822;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):H01L27/108 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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