| 摘要 |
PROBLEM TO BE SOLVED: To convert a continuous binary digit data series into an output codeword train of a 6 bits unit satisfying 7≤k≤12 with a (1, k) RLL (run length limited) rule after being converted into an input data word of a 4 bits unit and also to effectively suppress a DC component of the output codeword train by allowing DSV control without applying a redundant bit to the output codeword train. SOLUTION: The suppression of the DC component under the limitation of k=7 or 8 is performed by using an encoding table which can convert 4 bits into 6 bits with the (1, k) RLL rule without using the redundant bit. The continuation of a shortest bit inversion is interrupted to make it easy to be subjected to phase synchronization for extracting a clock used at the demodulation. COPYRIGHT: (C)2005,JPO&NCIPI
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