| 摘要 |
<p>The device has several standard processor body units (2-1,..,2-M) connected in parallel for executing commands in different threads, whereby each unit has at least one commend decoder unit (2'-1,..,2'-M) and a commend execution unit (2''-1,..,2''-M), several context memories (3-1-3N), each for temporarily storing a current processor state of a thread, whereby each context memory contains at least one register, and a thread control unit (4) that generates multiplexed control signals for switching the body units to the context memories for minimizing the probability of blocking of the multi-thread processor.</p> |
