发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem, wherein in a conventional PLL for use in control of a pulse-width modulation type converter apparatus, phase control cannot adapt quickly to the rapid fluctuations with respect to the frequency of a system power source. <P>SOLUTION: A PLL circuit is provided with a phase comparison circuit for detecting lagging or leading the phase differences; a phase integration circuit which counts up or down at each one cycle in a lagging or leading phase, accumulates the counted values, and converts the accumulated values into an analog voltage; and a voltage-controlled oscillation circuit for controlling an output frequency according with the analog voltage. In this PLL circuit, phase integration circuit is replaced by a phase proportional integration circuit, phase difference is converted into a numerical value by each cycle detected by the phase comparison circuit; and the converted numerical value is set to a positive value for the lagging phase and a negative value for the leading phase, the converted positive numerical value or negative value is multiplied by proportional gain coefficients to obtain a proportional value, a value which is obtained by multiplying the converted value by the integral gain coefficients is accumulated to obtain an integral value, the proportional value is added to the integral value to obtain a proportional integral value, and the proportional integral value is converted into an analog voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005204091(A) 申请公布日期 2005.07.28
申请号 JP20040008590 申请日期 2004.01.16
申请人 DAIHEN CORP 发明人 MOROTOMI NORIYUKI;SAKASHITA SHIYUUJI;MATSUISHI TAKEYOSHI
分类号 H02M7/48;H03L7/093 主分类号 H02M7/48
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