| 发明名称 |
System and method for modeling, abstraction, and analysis of software |
| 摘要 |
A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.
|
| 申请公布号 |
US2005166167(A1) |
申请公布日期 |
2005.07.28 |
| 申请号 |
US20050040409 |
申请日期 |
2005.01.21 |
| 申请人 |
NEC LABORATORIES AMERICA, INC. |
发明人 |
IVANCIC FRANJO;ASHAR PRANAV N.;GANAI MALAY;GUPTA AARTI;YANG ZIJIANG |
| 分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
