| 摘要 |
PROBLEM TO BE SOLVED: To provide a MOS transistor of nanometer scale that has reduced parasitic capacitance and junction leakage current by forming an SSR epi-channel, a silicon epi-layer, and a reverse spacer. SOLUTION: The transistor includes: an inversion epi-layer formed on a silicon substrate; a silicon epi-layer formed at the upper portion of the inversion epi-layer; a trench formed on the silicon epi-layer; a reverse spacer formed on the sidewall of the trench; a gate electrode formed at the upper portion of the epi-layer so as to have a predetermined width; a spacer formed on the sidewall of the gate electrode; an LDD region formed by overlapping a pocket region formed at the lower portion of the side face of the gate electrode and the inversion epi-layer at the upper portion thereof; a source/drain region formed at the lower portion of the LDD region and the side face of the spacer so as to be thicker than the LDD region; and a silicide formed at the upper portion of the silicon epi-layer and gate electrode at the upper portion of the source/drain. COPYRIGHT: (C)2005,JPO&NCIPI
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