发明名称 |
Semiconductor memory device having advanced test mode |
摘要 |
An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and-testing a write operation of the semiconductor memory device.
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申请公布号 |
US2005166097(A1) |
申请公布日期 |
2005.07.28 |
申请号 |
US20040882740 |
申请日期 |
2004.06.30 |
申请人 |
AN YONG-BOK |
发明人 |
AN YONG-BOK |
分类号 |
G01R31/28;G06F11/00;G11C29/00;G11C29/26;(IPC1-7):G06F11/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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