| 摘要 |
A bus communication system for enabling data transfer in synchronized communication is provided, which comprises master circuits, a slave circuit, a bus, and a bus arbitration circuit. Data transfer is performed between the master circuits and the slave circuit via the bus. When a transfer request is output from the master circuits, the right to occupy the bus is given to the master circuit which continuously outputs the transfer request to the same address, not more than a predetermined number of times continuously. When receiving the transfer request from the master circuit, the slave circuit informs the master circuit of the end of bus transfer and whether or not data transfer is ready. When informed that data transfer is ready, the master circuit ends data transfer, and when informed that data transfer is not ready, the master circuit outputs a transfer request to the slave circuit again.
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