Dynamic logic gate with relaxed timing requirements and output state holding,申请号EP19980108914-传众专利搜索

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发明名称	Dynamic logic gate with relaxed timing requirements and output state holding
摘要
申请公布号	EP0921639(B1)	申请公布日期	2005.07.27
申请号	EP19980108914	申请日期	1998.05.15
申请人	HEWLETT-PACKARD COMPANY	发明人	NAFFZIGER, SAMUEL D.
分类号	G01R31/28;H03K19/00;H03K19/096;(IPC1-7):H03K19/096;H03K19/017	主分类号	G01R31/28
代理机构		代理人
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