发明名称 |
Phase locked loop (PLL) frequency synthesizer and method |
摘要 |
A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.
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申请公布号 |
US6922110(B2) |
申请公布日期 |
2005.07.26 |
申请号 |
US20040884254 |
申请日期 |
2004.07.02 |
申请人 |
XYTRANS, INC. |
发明人 |
AMMAR DANNY F.;GRAHAM RONALD D. |
分类号 |
H03L7/23;(IPC1-7):H03L7/07;H03L7/16 |
主分类号 |
H03L7/23 |
代理机构 |
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主权项 |
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