发明名称 Method and apparatus for clock timing recovery in chiDSL particularly VDSL modems
摘要 Method and modem for fast timing recovery of transmitted data between a master chiDSL modem and a slave chiDSL modem, over a noisy, high loss, high distortion wiring. Transmitted QAM symbols are received and sampled at the slave modem. The sampled data is split into in-phase and quadrature channel, each of which is filtered by matched filter. The filtered outputs are sampled at twice the symbol rate and the lower and upper band edge components are extracted by modulating each of the sampled sequences of outputs with two discrete time sequences: cos(0.5 pi n)=. . . 1,0,-1,0 . . . and sin(0.5 pi n)=. . . 0,1,0,-1 . . . . Each of the resulting products is filtered with a first order low-pass filters and re-sampled again at the symbol rate. The Bit Error Rate is computed, and the slave modem switches from blind timing recovery mode, to data directed timing recovery mode, after the Bit Error Rate has sufficiently decreased.
申请公布号 US6922436(B1) 申请公布日期 2005.07.26
申请号 US20000623952 申请日期 2000.12.21
申请人 INFINEON TECHNOLOGIES AG 发明人 PORAT BOAZ;HARPAK AMNON;PELEG SHIMON
分类号 H03M1/66;H04L7/027;H04L27/38;(IPC1-7):H04B1/38;H03D3/18;H04L27/14 主分类号 H03M1/66
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