发明名称 ASIC architecture for active-compensation of a programmable impedance I/O
摘要 A method of, and a circuit for, impedance control. The method comprises the steps of providing an input/output cell having a controllable input/output impedance, providing a reference cell including a node having a variable voltage, and comparing the voltage of the node to a reference voltage. The voltage of the node is adjusted during a defined period and according to a defined procedure, and during that defined period, a digital signal is generated. That digital signal is transmitted to the input/output cell to adjust the input/output impedance. Preferably, the circuit is embodied as a digital controller designed as a synthesized core or macro. The advantage of this implementation is that it never has to be redesigned in future technologies. The digital controller may be carried over to future technologies in the form of VHDL code, which is pure logic and independent of technology.
申请公布号 US6922074(B2) 申请公布日期 2005.07.26
申请号 US20020072165 申请日期 2002.02.07
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 COUGHLIN, JR. TERRY C.;WANG GEOFFREY
分类号 G06F3/00;H03K19/00;H03K19/0175;(IPC1-7):H03K17/16;H03K19/003 主分类号 G06F3/00
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