发明名称 Method of power consumption reduction in clocked circuits
摘要 A method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is provided. A first latch, within the plurality of latches, is located which has more than a predetermined slack. The possibility of substituting an available second latch, that requires less power to operate, is then determined, subject to the constraint that the slack after substitution should still be positive, although it may be less than the predetermined number mentioned above. Where such a possibility is determined to exist, the first latch is then replaced with the available second latch.
申请公布号 US6922818(B2) 申请公布日期 2005.07.26
申请号 US20010833429 申请日期 2001.04.12
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHU SAM GAT-SHANG;CLABES JOACHIM GERHARD;GOULET MICHAEL NORMAND;ROSSER THOMAS EDWARD;WARNOCK JAMES DOUGLAS
分类号 G06F1/10;G06F1/12;G06F17/50;H03K3/037;(IPC1-7):G06F17/50 主分类号 G06F1/10
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