发明名称 |
System and method for achieving timing closure in fixed placed designs after implementing logic changes |
摘要 |
A system and method for implementing logic changes in integrated circuits (ICs). In a preferred embodiment, donor logic elements are taken from donator logic paths. The donated cells are implemented into a logic path altered by an ECO. The donated cell is replaced by spare cells. Timing analysis is done to ensure all logic paths are timing closed.
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申请公布号 |
US6922817(B2) |
申请公布日期 |
2005.07.26 |
申请号 |
US20030408205 |
申请日期 |
2003.04.04 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
BRADFIELD TRAVIS ALISTER;SPITLER TRACY ROBERT;JOHNSON GREGORY A.;MOTIFF MATTHEW RICHARD |
分类号 |
G06F9/45;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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