发明名称 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method for forming metal wiring of a semiconductor device which reduces an RC (resistor and capacitor) delay time and realizes the metal wiring of high reliability, by suppressing a crosstalk phenomenon between the metal wiring and decreasing a capacitance between the metal wires in the next generation high-performance of close integrated semiconductor device, in spite of using aluminum or aluminum alloy inferior in a fundamental material property in comparison with copper as a metal wiring material. SOLUTION: The method includes steps of: forming many thickly gathered metal wiring on a substrate with many contact plugs formed thereon in a reactive ion etching process where a hard mask pattern composed of a low-k dielectric insulator is used, forming a barrier metal layer on the side walls of the many metal wiring; forming an inter-layer insulating layer composed of a low-k dielectric insulator on the whole structure where the barrier metal layer is formed. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005197637(A) 申请公布日期 2005.07.21
申请号 JP20040189667 申请日期 2004.06.28
申请人 HYNIX SEMICONDUCTOR INC 发明人 RYU HYUN KYU
分类号 H01L21/28;H01L21/322;H01L21/44;H01L21/4763;H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/768 主分类号 H01L21/28
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