发明名称 POWER-UP CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a power-up circuit of a semiconductor memory device which can prevent unnecessary reset of a power-up signal by power drops and also can assure a margin required for stable initialization of internal logics of the memory. SOLUTION: A power-up circuit includes a power supply voltage level follower unit for outputting a first bias voltage and a second bias voltage which linearly increase or decrease in proportion to a power supply voltage; a first power supply voltage detecting unit for detecting a first critical voltage level where a logic level of a power-up signal is changed in response to the first bias voltage when the power supply voltage decreases; a second power supply voltage detecting unit for detecting a second critical voltage level where a logic level of the power-up signal is changed in response to the second bias voltage when the power supply voltage increases; and a trigger unit for inverting an output signal of the trigger unit in response to one of a first detection signal outputted from the first power supply voltage detecting unit when the power supply voltage decreases and a second detection signal outputted from the second power supply voltage detecting unit when the power supply voltage increases, wherein the second critical voltage level is higher than the first critical voltage level. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005196929(A) 申请公布日期 2005.07.21
申请号 JP20040096633 申请日期 2004.03.29
申请人 HYNIX SEMICONDUCTOR INC 发明人 DO CHANG-HO
分类号 G11C11/413;G11C5/00;G11C5/14;G11C7/00;G11C11/4072;H03K17/22;(IPC1-7):G11C11/413 主分类号 G11C11/413
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