| 摘要 |
An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits ( 1 ) to perform arithmetic processing based on input analog signals, a capacitor ( 2 ) to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits ( 1 ), an A/D conversion circuit ( 3 ) to convert the charge amount stored in the capacitor ( 2 ) to digital data, and a digital arithmetic circuit ( 4 ) to calculate a cumulative value based on the converted digital data.
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