发明名称 |
Method of forming a metal gate in a semiconductor device |
摘要 |
In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.
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申请公布号 |
US2005158935(A1) |
申请公布日期 |
2005.07.21 |
申请号 |
US20050037506 |
申请日期 |
2005.01.18 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
SHIN JEONG-HO;AHN JONG-HYON;CHEONG KONG-SOO;JUN JIN-WON |
分类号 |
H01L21/28;H01L21/3205;H01L21/336;H01L21/8234;H01L29/423;H01L29/78;(IPC1-7):H01L21/336;H01L21/823;H01L21/320 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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