<p>A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.</p>
申请公布号
WO2005066968(A1)
申请公布日期
2005.07.21
申请号
WO2004US43496
申请日期
2004.12.22
申请人
INTEL CORPORATION;ELLIS, ROBERT, M.;MOONEY, STEPHEN, R.;KENNEDY, JOSEPH, T.
发明人
ELLIS, ROBERT, M.;MOONEY, STEPHEN, R.;KENNEDY, JOSEPH, T.