| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a programmable frequency divider for a phase lock loop having a latch circuit with a first input receiving a program integer and an output deriving a latch integer. <P>SOLUTION: A phase lock loop monitors a first digital signal and derives a second digital signal operating substantially at a frequency in-phase with the first digital signal. A programmable divider latches a program integer for deriving a latch integer, compares the latch integer to a certain integer, and derives a flag signal having a first state when the latch integer mismatches the certain integer or a flag signal having a second state when the latch integer matches the certain integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for deriving the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for deriving a lock detection signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
