发明名称 Method for manufacturing bit line contact structure of semiconductor memory
摘要 A method is disclosed for manufacturing bit line contact structures of semiconductor memories. The manufacturing method comprises the steps of providing a semiconductor substrate, forming a plurality of gates on the surface of the substrate, applying a first insulating layer to cover the surface of the substrate and the gates, selectively forming a plurality of gate contact windows at the locations of the gates, selectively forming bit line contact windows in the first insulating layer, the bit line contact windows contacting the substrate, and filling the gate contact windows and the bit line contact windows with a conductive layer.
申请公布号 US2005158972(A1) 申请公布日期 2005.07.21
申请号 US20040759058 申请日期 2004.01.20
申请人 NANYA TECHNOLOGY CORPORATION 发明人 LIN FENG-CHUAN;CHEN YI-NAN;HSU PING
分类号 H01L21/3205;H01L21/60;H01L21/8242;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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