发明名称 METHOD FILLING VIA IN SILICON SUBSTRATE
摘要 PROBLEM TO BE SOLVED: To provide a metallization process for metallizing a blind via or a through via formed in a silicon, and provide a material system. SOLUTION: The process comprises a step of forming a composition, namely, a suspension with a small thermal expansion coefficient compared to pure metal (such as copper, silver, and gold); and a step of filling a via hole formed in the silicon 3 by using the suspension, namely, a paste, then sintering the suspension. As a result of the sintering, a highly conductive structure is formed, with the shrink of a capacity retained at a minimum, without forming any macroscopic void. The suspension is so selected that the thermal expansion coefficient of the suspension maintains a value close to the thermal expansion coefficient of the silicon 3. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005197733(A) 申请公布日期 2005.07.21
申请号 JP20050000204 申请日期 2005.01.04
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 CASEY JON A;SUNDLOF BRIAN R
分类号 H01L23/12;H01B1/16;H01L21/00;H01L21/02;H01L21/44;H01L21/48;H01L21/768;H01L23/48;H05K1/09;H05K3/40;H05K3/46;(IPC1-7):H01L23/12 主分类号 H01L23/12
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