发明名称 METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT WITH REDUCED POWER SOURCE NOISE
摘要 PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit to reduce power source noise by taking the frequency characteristic of the power source noise into consideration. SOLUTION: The impedance of power wiring is calculated on the basis of the design data of the semiconductor integrated circuit and the frequency characteristic of the impedance calculated is determined. Based on the frequency characteristic determined, the design of the semiconductor integrated circuit is changed. The impedance between power sources of different potentials, as between a power supply and ground, may be calculated. Alternatively, the impedance between power sources of approximately the same potential, as between a power supply and an N-well power supply, may also be calculated. When the design is changed, a wiring method, the kind of package, the characteristic of an inductance element, a base structure, wiring intervals, decoupling capacity, wiring length, the characteristic of a resistance element and the like are changed. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005196406(A) 申请公布日期 2005.07.21
申请号 JP20040001347 申请日期 2004.01.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIMAZAKI KENJI;KOJIMA SEIJIRO;HIRANO SHOZO;SATO KAZUHIRO;TAKAHASHI MASARO;ICHINOMIYA TAKAHIRO;TSUJIKAWA HIROYUKI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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