Multithread processor architecture for triggered thread switching without any clock cycle loss, without any switching program instruction, and without extending the program instruction format

摘要

A multithread processor based on the inventive architecture is a clocked multithread processor ( 1 ) for data processing of N threads by means of a standard processor root unit ( 2 ), wherein a thread T_j which is to be processed at any given time by the standard processor root unit ( 2 ) can be switched without any clock cycle loss by means of a switching trigger signal (UTS) to another thread T₁, wherein the switching trigger signal (UTS) is generated as a consequence of a program instruction (which is fetched from a program instruction memory ( 3 ) and implies a latency time) for the thread T_j which is to be processed at that time and results in a latency time for the standard processor root unit ( 2 ), before the program instruction which has been fetched and implies a latency time is decoded by the standard processor root unit ( 2 ).