发明名称 STANDBY POWER REDUCING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a standby power reducing circuit which is low in power consumption by a simple structure without using a microcomputer etc., and has no delay of reception resuming when an intermittent operation is required. <P>SOLUTION: The device has a digital transmission apparatus 1 provided with a pulse output terminal 1B for receiving an analog or digital signal and outputting a digital pulse signal during receiving this signal, and an enable/disable terminal 1A; and a detection generating circuit 2 using the digital pulse signal as an input for performing pulse detection for this input and level generation, and transmitting a control signal to the enable/disable signal terminal 1A of the apparatus 1. The circuit 2 generates a control signal for determining the presence or absence of the digital pulse signal, and bringing an operation of the apparatus 1 into an enable state if the digital pulse signal is present and into a disable state if the signal is not present. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005197865(A) 申请公布日期 2005.07.21
申请号 JP20040000230 申请日期 2004.01.05
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KAWANO RYUSUKE;MATSUTANI YASUYUKI
分类号 H04B10/11;H04B10/07;H04B10/116 主分类号 H04B10/11
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