| 摘要 |
A semiconductor device for testing memory, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, and a fail detector for determining memory failure. Another semiconductor device for testing at least one of a plurality of memory devices, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, a reference data generator for generating reference data, and a fail detector for determining memory failure. A method of determining memory failure, including writing data to a plurality of memory devices, reading the data from the plurality of memory devices, comparing corresponding addresses of the read data simultaneously, outputting a single fail signal when the comparing step determines at least one of the read data from the plurality of memory devices as not being equal. A semiconductor device for testing memory, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, a reference data generator for generating reference data, a selection circuit for selecting the read data from one of the plurality of memory devices, and a comparator for comparing the read data from one of the plurality of memory devices with the reference data. A semiconductor device for testing memory, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, and a single comparison unit for determining memory failure in at least two of the plurality of memory devices. A method of determining memory failure, including writing data to a plurality of memory devices, reading the data from the plurality of memory devices, comparing corresponding addresses of the read data of at least two of the plurality of memory devices in a single comparison unit.
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