| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To delay a reference clock for data capture with a high frequency clock of a memory controller. <P>SOLUTION: The memory controller has multiple clock generating means for generating a multiple clock and system clock generating means for dividing the multiple clock to generate a system clock, sends the system clock as a memory clock to a clock-synchronous memory, and sends a control signal, an address signal and a writing date signal to the clock-synchronous memory generated synchronously with the system clock, to the clock-synchronous memory; and has data capture clock generating means for capturing the memory clock sent to the clock-synchronous memory as a reference clock for a data capture clock for data reading, and latching the data capture reference clock with the multiple clock to generate the data capture clock delayed by a predetermined shift from the data capture reference clock, and captures data from the clock-synchronous memory at the data capture clock. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
