发明名称 Time sharing a single port memory among a plurality of ports
摘要 An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.
申请公布号 US6920510(B2) 申请公布日期 2005.07.19
申请号 US20020163047 申请日期 2002.06.05
申请人 LSI LOGIC CORPORATION 发明人 CHANG GARY;SU HONG-MEN
分类号 G06T9/00;(IPC1-7):G06F3/00;G06F3/06;G06F5/00 主分类号 G06T9/00
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