发明名称 Clock down sensor
摘要 A clock down sensor mainly comprises a converter and a low-pass filter. The converter is used to convert an input signal from a PECL (Positive Emitter Coupling Logic) signal to a TTL (Transistor Transistor Logic) signal, the low pass filter is used to obtain a DC (Direct Current) level of the TTL signal. Thereby, the sensor can judge whether the clock signal is terminated according to the potential of the output signal in order to emit a warning so that a breakdown elimination inquiry can be done or automatic breakdown elimination can be processed earlier.
申请公布号 US6919741(B2) 申请公布日期 2005.07.19
申请号 US20030717581 申请日期 2003.11.21
申请人 ASIA OPTICAL CO., LTD 发明人 YANG CHANG YI
分类号 G06F1/04;H03K5/19;(IPC1-7):H03K5/19 主分类号 G06F1/04
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