| 摘要 |
PROBLEM TO BE SOLVED: To shorten processing time of read request at the case when a processor issues requests to a memory successively in a system having single processor constitution. SOLUTION: In an interface circuit (10) which performs data communication between an MPU (Micro Processing Unit)(100) and a DRAM (Dynamic Random Access Memory) (200), an MPU interface (11) transmits to a request transmitter (12) the read requests received from the MPU (100) and following requests received from the MPU (100) during the time from outputting request acknowledge to the read request till outputting data acknowledge. The request transmitter (12), while storing the given read request and the following requests to two storages (13, 14) respectively, transmits these requests to a DRAM interface (15) in order. The DRAM interface (15) performs pipeline processing of the given requests. COPYRIGHT: (C)2005,JPO&NCIPI
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