发明名称 REFERENCE VOLTAGE GENERATING CIRCUIT AND ERRONEOUS OUTPUT PREVENTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit for detecting a decrease in a reference voltage to be outputted, and for outputting a signal for fixing a control logic when the reference voltage decreases. SOLUTION: A reference voltage generating circuit 1 including an output stage for outputting a predetermined reference voltage based on a band gap voltage is provided with a logic fixed signal outputting means 1c for detecting that a predetermined reference voltage is not outputted due to a decrease in a power source voltage, and for outputting the detection signal as a signal for fixing a control logic used when the reference voltage decreases. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005189927(A) 申请公布日期 2005.07.14
申请号 JP20030427272 申请日期 2003.12.24
申请人 FUJITSU TEN LTD 发明人 KOMATSU KAZUHIRO;KIDO KEISUKE;NISHIDA YUSUKE
分类号 G05F1/10;(IPC1-7):G05F1/10 主分类号 G05F1/10
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