发明名称 |
Scalable logic self-test configuration for multiple chips |
摘要 |
A scalable LBIST control structure provides for testing of multiple independent clock domains within a chip and/or across multiple chips. The LBIST control structure sequences all clock domains through each step of the LBIST sequence synchronously, allowing multiple clock domains and/or multiple chips to be controlled from a common point.
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申请公布号 |
US2005155003(A1) |
申请公布日期 |
2005.07.14 |
申请号 |
US20040753852 |
申请日期 |
2004.01.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORTION |
发明人 |
RICH MARVIN J.;HERRING JAY R. |
分类号 |
G01R31/3185;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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