发明名称 |
Low stress sidewall spacer in integrated circuit technology |
摘要 |
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
|
申请公布号 |
US2005153496(A1) |
申请公布日期 |
2005.07.14 |
申请号 |
US20040756023 |
申请日期 |
2004.01.12 |
申请人 |
NGO MINH V.;CHAN SIMON S.;BESSER PAUL R.;KING PAUL L.;RYAN ERROL T.;CHIU ROBERT J. |
发明人 |
NGO MINH V.;CHAN SIMON S.;BESSER PAUL R.;KING PAUL L.;RYAN ERROL T.;CHIU ROBERT J. |
分类号 |
H01L21/336;(IPC1-7):H01L21/336;H01L21/476 |
主分类号 |
H01L21/336 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|