发明名称 RECORDING MEDIUM AND CIRCUIT SIMULATION METHOD
摘要 PROBLEM TO BE SOLVED: To reduce errors between actually measured values of element characteristics of a high-breakdown voltage MOS transistor having a low-concentration impurity area between a channel area and a drain electrode, and simulation values. SOLUTION: An element model of a high-breakdown voltage MOS transistor (1) having a low-concentration impurity area (5) between a channel area (2) and a drain electrode (4) is defined by combining a plurality of element models. Fundamental characteristics are represented by a standard MOS model (MMAIN). A conductivity modulation effect of a low-concentration drain diffusion layer is represented by a variable resistance model (RDD) which has a value varied by a drain voltage and a gate voltage. A gate-drain overlap capacity is represented by a MOS capacity (MCAP) between gate-bulks. The variable resistance model compensates the variance of a voltage in a channel end part adjacent to the low-concentration diffusion layer, which is caused by an influence of not only the gate voltage but also the drain voltage. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005190328(A) 申请公布日期 2005.07.14
申请号 JP20030433091 申请日期 2003.12.26
申请人 RENESAS TECHNOLOGY CORP 发明人 SAITO TAKASHI;SUGIHARA HITOSHI;KOBAYASHI TOSHIKO
分类号 G06F17/50;H01L21/336;H01L21/82;H01L29/76;H01L29/78;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址