发明名称 |
Consistency evaluation of program execution across at least one memory barrier |
摘要 |
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier. A request engine may provide an updated data fill corresponding to an invalid cache line. The invalid cache line may be associated with at least one executed load instruction. A load compare component may compare the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction.
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申请公布号 |
US2005154832(A1) |
申请公布日期 |
2005.07.14 |
申请号 |
US20040756534 |
申请日期 |
2004.01.13 |
申请人 |
STEELY SIMON C.JR.;TIERNEY GREGORY E. |
发明人 |
STEELY SIMON C.JR.;TIERNEY GREGORY E. |
分类号 |
G06F12/00;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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