A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption is met.
申请公布号
WO2005008672(A3)
申请公布日期
2005.07.14
申请号
WO2004US22679
申请日期
2004.07.13
申请人
FULCRUM MICROSYSTEMS, INC.;CUMMINGS, URI;LINES, ANDREW