Shrunk low on-resistance DMOS structure

摘要

The on resistance per unit area of integration of a DMOS structure is reduced beyond the technological limits of a mask that is defined based upon the continuity of a heavily doped superficial silicon region along the axis of the elongated source island openings through the polysilicon gate layer in the width direction of the integrated structure. The mask no longer needs to be defined with a width (in the pitch direction) sufficiently large to account for the overlay of two distinct and relatively critical masks. These two masks are the source implant mask and the body contacting plug diffusion implant contact opening mask. Such a constraint of the prior techniques restricting the opening through the polysilicon gate layer to safely ensure an appropriate distance of the body connection plug diffusion dopant profile from the definition edges of the polysilicon is overcome by defining the body connection plug diffusion implant area by way of a mutual orthogonality between two no longer critical masks that may both be defined at minimum linewidth of the fabrication process.