发明名称 Video decoder
摘要 A control device, system and method for multi-pixel reading provides a processor receiving multi-pixel, uses memory units wherein each memory unit sequentially receiving a writing enable signal, and then receiving and storing multi-pixel. Simultaneously, the processor having multi-data bus receives multi-pixel of the each memory unit output. The clock of the enabling all the memory units is less then the delay of the processor reading, so that reducing the spare time of the image decoding system and reducing the reading time of the reading image.
申请公布号 US2005152609(A1) 申请公布日期 2005.07.14
申请号 US20040001636 申请日期 2004.12.02
申请人 VIA TECHNOLOGIES, INC. 发明人 WANG ROY;WANG DAVID
分类号 G06F7/38;G06F7/52;G06F13/00;G06F17/10;G06F17/14;G06K9/36;G06T1/00;G06T9/00;H03M7/30;H04N1/46;H04N7/12;H04N7/26;H04N7/30;H04N7/50;(IPC1-7):G06K9/36 主分类号 G06F7/38
代理机构 代理人
主权项
地址